The present invention relates, in general, to the field of integrated circuit ("IC") devices. More particularly, the present invention relates to a technique for integrating the internal clock signal and functional commands in IC devices utilizing an externally supplied clock signal and requiring a positive set-up time to discern and/or execute commands. The technique of the present invention is especially advantageous when implemented in conjunction with memory ICs, including synchronous dynamic random access memory ("SDRAM") devices.
In many integrated circuit devices utilizing an externally supplied clocking signal, a relatively large clock buffer is typically utilized to amplify, or "buffer", the signal to then drive a derivative internal clock signal which is routed to various of the IC's command executing portions. Commands directing the IC to then execute a specific function are then compared against the internal clock signal and executed if the resultant logic is correct. This is an inherently slow process inasmuch as the clock must first be "buffered up" (i.e. amplified) in order to drive the relatively large capacitance of the on-chip clock network with more speed reducing gate delays being added in ultimately deciding which commands to execute.